Current PhD Students
I am a 3rd year PhD student working in Tufts Computer Architecture Lab (TCAL) with Professor Mark Hempstead. Before joining TCAL, I worked with Professor Shahin Hesabi at Sharif University for my MS in computer engineering and got my BS in computer engineering from Amir Kabir university. My research interest includes the use of AI in design and improvement of computer architecture, and hardware specialization of machine learning applications.
Cesar is a 3rd year PhD Candidate, research assistant in the Tufts Computer Architecture Lab, and a 2014 National GEM Consortium PhD Fellow. He received his Bachelor of Science in Computer Engineering from Howard University in 2010, and his Master of Science in Computer Engineering from Drexel University in 2015. Cesar’s research interests lie in memory systems, specifically in the effective usage of cache hierarchies. Cesar researches replacement/insertion/promotion policies and prefetching techniques in last level caches, analyzes cache needs on a per workload basis, and studies workload properties in shared caching paradigms. Cesar has interned with IBM where he validated memory bus logic and researched dynamic command issue request rate modulation.
Alex is a 3rd-year PhD candidate and research assistant in TCAL. His research encapsulates a broad range of topics including Non-Volatile Memory Based Caches, Image Signal Processing Accelerators, and Power/Thermal-Aware Architecture. Alex arrived at Tufts in 2012 and completed the B.S. degree in Computer Engineering (with a minor in Mathematics) and the M.S. degree in Electrical Engineering in 2017 as part of a 5-year combined B.S. and M.S. degree program. He joined TCAL in 2016 and began his Masters project research on the impact of replacing SRAM with emerging Non-Volatile Memory technologies in the Last-Level Cache. His dissertation research is centered around Hotspot mitigation in modern chips. In the Winter and Spring of 2019, Alex was a Hardware Engineering Intern at Google in Mountain View, CA where he worked on the Pixel Visual Core, a novel 3.1 TOPS programmable Image Processing architecture (IPU) for the Google Pixel Phone.
Drexel University (co-advised with Baris Taskin)
Mike is a PhD candidate at Drexel’s VLSI and Architecture Lab (VANDAL). His research has focused on capturing application-specific characteristics to guide the hardware design process. This has included custom tools for measuring compute, communication, and both explicit and implicit synchronization. These tools have been used for a spectrum of studies, including large design-space exploration of the uncore, communication characterization for workload partitioning, NBTI reliability analysis and NoC design for reliability, and more recently near-memory system design. Mike is advised by Dr. Baris Taskin of Drexel University and Dr. Mark Hempstead of Tufts University. In addition to his research interests, he also has a strong passion for education, taking leading roles in Drexel University’s ECE curriculum and being a frequent volunteer at CodedByKids’ Philadelphia community program. Before starting his PhD, Mike worked at Intel on media encoders and decoders. He is interning at Facebook for the fall of 2019, focusing on profiling and optimization methodologies for emerging AI platforms.
Parnian is a 4th year Ph.D student at Tufts. She works in Tufts Computer Architecture Lab (TCAL) under Dr. Mark Hempstead supervision. Her research focuses on finding new methodologies to design efficient accelerators and heterogeneous architectures. She is passionate about projects that combine fields together and solve immediate problems through true engineering solutions.
Drexel University (co-advised with Baris Taskin)
Karthik “Paco” is a PhD candidate in Drexel Computer Engineering, whose research interests involve multi-disciplinary concepts such as computer architecture, high performance computing (HPC), communication networks on chip (NoC), and heterogeneous computing. Advised by Dr. Baris Taskin (Drexel VANDAL) and Dr. Mark Hempstead (Tufts Computer Architecture Lab), Paco’s research investigates network-on-a-chip designs as potential solutions to enable efficiently processing within large scale (100s to 1000s of cores) chip multiprocessors. The goal of the research is to develop cutting edge NoC designs that will cater to future exascale computing workloads used in industry and the research community. Paco received the NSF Graduate Research Fellowship in 2014 and has been a Fellowships Ambassador since 2015. In addition to his research, Paco has been a mentor for ECE senior design groups, a teaching assistant for ECE courses including computer architecture, and the President of the Drexel IEEE Graduate (DIG) Forum. He also has interned at ARM Research where he investigated simulation techniques to efficiently model high performance computing platforms.