Many-Accelerator Computing

This NSF CAREER project, “Combating Dark Silicon with Tiled Many-Accelerator Architectures”, aims to address the challenges of increasing transistor power-density in modern microprocessors that limits performance and threatens the future of computing. We are investigating the use of specialized accelerator cores, each designed to compute one particular application 10-100 times more efficiently than general purpose core, to combat the increase of Dark Silicon. The project has two main aspects: (1) accelerator selection algorithms, designed to improve the coverage of the application by accelerators. These algorithms and methodologies will be tested through the design of canonical tiles of accelerators each tile and the accelerators on that tile are designed to accelerate a particular application domain; (2) the design of memory systems and interconnect that can provide the high-amount of bandwidth and storage to accelerators that are active only occasionally.

This effort is to make many-accelerator architectures more general and available for a wide range of devices and applications. We are currently studying Internet-of-Things (IoT) workloads, imaging workloads, and high-performance computing applications.

Because the performance of modern systems is limited by cost of communicating between accelerator cores, project uses the PI’s prior work on communication classification and Sigil workload characterization tool and the Accelerator Store.


Stay tuned as we develop these new methodologies and memory systems.


“CAREER: Combating Dark Silicon through Specialization: Communication-Aware Tiled Many-Accelerator Architectures” 2/1/2014 – 1/31/2019. $470,000. National Science Foundation (NSF)


  • D. Werner, M. Hempstead, K. Juretus, and I. Daulagala, “The Vulnerability of Specialized Architectures to Temperature Side-Channel Information Leakage,” Boston Area Architecture Workshop (BARC), Jan. 2016.
  • P. Mokri and M. Hempstead, “Stockpile Of Accelerators: A Methodology To Increase Accelerators’ Coverage”, Boston Area Architecture (BARC) Workshop, January 2016.
  • Steven Battle and Mark Hempstead, Characterizing the Costs and Benefits of Hardware Parallellism in Accelerator Cores, Proceedings of the International Conference on Computer Design (ICCD), Asheville, NC Oct 2013.
  • Siddharth Nilakantan, Steven Battle, Mark Hempstead Metrics for Early-Stage Modeling of Many-Accelerator Architectures, Computer Architecture Letters (CAL) . July-Dec 2012
  • M. Lyons, M. Hempstead, D. Brooks, G.-Y. Wei The Accelerator Store Framework for High-Performance, Low-Power Accelerator-based Systems ACM Transactions on Architecture and Code Optimization (TACO). Joint Presentation at HiPEAC, Paris France. January, 2012