As technology advances, transistor size shrinks; which causes higher energy density on a chip to the point that  makes Moor’s law irrelevant. One way to battle this is to use hardware accelerators in designs. Accelerators, in broad sense, are application specific hardware [1].

In 2014, however, up to a third of cellphone chips are dedicated to accelerators. It is not hard to see the inefficiency of this approach in long run in regards to area and power usage. One way to avoid area and power limitation of this approach is to run similar codes on the same accelerator, instead of designing application specific accelerator. Each accelerators should be general enough to accelerate multiple applications yet specific enough to accelerate the runtime of each application; this concept is called the coverage. Conventional approach to detect full coverage, either fails to optimally exploit applications’ similar critical paths or results in smaller ALUs without appreciating the complex control structure of applications [1] [2] [3].

Our team aims to devise new methodologies to address challenges computer architects face designing these systems. This project branches into two sub-projects: 1. Designing many accelerator architecture 2. Designing memory interface of many accelerator  architectures.



[1] J. Cong, M. Ghodrat, M. Gill, B. Grigorian, H. Huang, and G. Reinman, “Composable accelerator-rich microprocessor enhanced for adaptivity and longevity,” in 2013 IEEE International Symposium on Low Power Electronics and Design (ISLPED), Sep. 2013, pp. 305–310.

[2] B. Reagen, R. Adolf, Y. Shao, G.-Y. Wei, and D. Brooks, “MachSuite: Benchmarks for accelerator design and customized architectures,” in 2014 IEEE International Symposium on Workload Characterization (IISWC), Oct. 2014, pp. 110–119.

[3] J. Benson, R. Cofell, C. Frericks, C.-H. Ho, V. Govindaraju, T. Nowatzki, and K. Sankaralingam, “Design, integration and implementation of the DySER hardware accelerator into OpenSPARC,” in 2012 IEEE 18th International Symposium on High Performance Computer Architecture (HPCA), Feb. 2012, pp. 1–12.