4. Shared Accelerator System on Chip

This system infrastructure will run multiple shared accelerators on a SoC connected by a system bus; include a framework to connect different hardware interfaces; include a general purpose CPU that will program and interact with the shared accelerators and an operating system. The infrastructure will make it possible to measure the costs and benefits of Shared Accelerators in the system.

For now, we use AXI4 to connect different modules to each other. AXI is part of ARM AMBA, a family of microcontroller buses first introduced in 1996. The first version of AXI was first included in AMBA 3.0, released in 2003. AMBA 4.0, released in 2010, includes the second major version of AXI, AXI4. There are three types of AXI4 interfaces:

  • AXI4: For high-performance memory-mapped requirements.
  •  AXI4-Lite: For simple, low-throughput memory-mapped communication (for example, to and from control and status registers).
  •  AXI4-Stream: For high-speed streaming data.