| Hardware acceleration of common application tasks can provide significant advantages in chip performance and reduce energy consumption. Embedded processor architectures that utilize accelerators must carefully balance cost, power, and performance constraints. In the space of microcontroller-based System-on-Chip (SoC) systems, many designs include large private memories within each hardware accelerator that contribute to leakage power, require significant area, and add additional overhead when transferring state between accelerators. We have built accelerator store, a shared memory framework for hardware accelerator based architectures.[CAL’10][TACO’12]Collaborators: Mike Lyons |
