Current Students

Current PhD Students

Cesar Gomes

Cesar is a 3rd year PhD Candidate, research assistant in the Tufts Computer Architecture Lab, and a 2014 National GEM Consortium PhD Fellow. He received his Bachelor of Science in Computer Engineering from Howard University in 2010, and his Master of Science in Computer Engineering from Drexel University in 2015. Cesar’s research interests lie in memory systems, specifically in the effective usage of cache hierarchies. Cesar researches replacement/insertion/promotion policies and prefetching techniques in last level caches, analyzes cache needs on a per workload basis, and studies workload properties in shared caching paradigms. Cesar has interned with IBM where he validated memory bus logic and researched dynamic command issue request rate modulation.

Alexander Hankin

Alex is a 2nd-year, post-Quals PhD student, and his work is centered around emerging Non-Volatile Memory (NVM) technologies–such as Spin-Torque Transfer RAM (STT-RAM) and Resistive RAM (ReRAM)–to assess their potential for adoption in (traditionally) SRAM-based last-level cache. He completed┬áhis B.S. degree in Computer Engineering with a minor in Mathematics in 2016, and his M.S. degree in Electrical Engineering in 2017, both at Tufts as part of a 5-year combined B.S. and M.S. He is currently a Hardware Engineering Intern at Google in Mountain View, CA where he does research on the Pixel Visual Core, a novel 3.1 TOPS programmable Image Processing architecture (IPU) for the Google Pixel Phone.

Mike Liu,
Drexel University (co-advised with Baris Taskin)

Maziar Mehdizadehamiraski

Parnian Mokri

Karthik Sangaiah,
Drexel University (co-advised with Baris Taskin)

Karthik “Paco” is a PhD candidate in Drexel Computer Engineering, whose research interests involve multi-disciplinary concepts such as computer architecture, high performance computing (HPC), communication networks on chip (NoC), and heterogeneous computing. Advised by Dr. Baris Taskin (Drexel VANDAL) and Dr. Mark Hempstead (Tufts Computer Architecture Lab), Paco’s research investigates network-on-a-chip designs as potential solutions to enable efficiently processing within large scale (100s to 1000s of cores) chip multiprocessors. The goal of the research is to develop cutting edge NoC designs that will cater to future exascale computing workloads used in industry and the research community. Paco received the NSF Graduate Research Fellowship in 2014 and has been a Fellowships Ambassador since 2015. In addition to his research, Paco has been a mentor for ECE senior design groups, a teaching assistant for ECE courses including computer architecture, and the President of the Drexel IEEE Graduate (DIG) Forum. He also has interned at ARM Research where he investigated simulation techniques to efficiently model high performance computing platforms.

Guru Prasad Srinivasa,
University at Buffalo (advised by Geoffery Challen)

David Werner