Power-Agile Computing

Power-Agile Computing
Battery-powered devices are trapped by trends. Better performance requires more power, battery technologies are improving slowly, and users want their devices to last as long as they do today or longer. A way to escape this trap is to design energy proportional devices leveraging power-proportional hardware architectures that deliver good performance when needed and consume little power when idle. Design of energy proportional devices is hampered by the abstraction of application, operating system and hardware component designs from each other. The goal of power-agile computing project is to come up with new definitions and algorithms to guide hardware software co-design process. In the process, we define energy proportionality formally and introduce the concept of power agility. We come up with cross-layer interfaces; application and operating system layers, and operating system and hardware layers. We are working towards using these interfaces to tune individual hardware components power settings in order to achieve overall system energy proportionality.Because most device components are tuned to operate efficiently within a narrow power-performance range, we expect future power-proportional architectures to be increasingly heterogeneous: featuring multiple different processors, memory banks, storage devices and radios, each component embodying a particular power-performance tradeoff. Heterogeneity will produce a single device that can morph into many others: phones that can sprint like a laptop and sleep like a sensor node.

This is a collaboration with the Blue research group at University at Buffalo

Contributors: Geoffrey Challen http://www.cse.buffalo.edu/people/?u=challen

Funding:

“CSR: Medium: Collaborative Research: Architecture and System Support for Power-Agile Computing.” 8/1/2014 – 7/31/2016. $278,836 (Drexel Portion). National Science Foundation (NSF)

Publications:

  • Rizwana Begum, Guru Prasad Srinivasa, David Werner, Mark Hempstead and Geoffrey Challen. Energy-Performance Trade-offs on Energy-Constrained Devices with Multi-Component DVFS. Accepted for publication in IEEE International Symposium on Workload Characterization (IISWC), Oct 2015.
  • Rizwana Begum and Mark Hempstead. Power Agility Metrics: Measuring Dynamic Characteristics of Energy Proportionality. Accepted for publication in the International Conference on Computer Design (ICCD). Oct 2015.
  • Rizwana Begum, Mark Hempstead, Guru Prasad, and Geoffery Challen, New Interfaces for Achieving Power Agility on Mobile Devices, HotMobile, Feb 2014
  • Geoffrey Challen, Mark Hempstead. The Case for Power-Agile Computing USENIX Workshop on Hot Topics in Operating Systems (HotOS). Napa, CA., May 2011

 

Figure 1: Example of component proportionality and overall device agility we are striving to achieve.

Figure 2: Power envelopes of all 144 example device component ensemble for a device with two processors, memory, storage and radio components.

Figure 3: Per-component energy breakdown for 77 real smartphones collected in PhoneLab. See also: PhoneLab project website: http://www.phone-lab.org/

Figure 4: Relationship between current, CPI, and CPU utilization.