Lillian Pentecost*, Harvard University
Alexander Hankin*, Tufts University
Marco Donato, Tufts University
Mark Hempstead, Tufts University
Gu-Yeon Wei, Harvard University
David Brooks, Harvard University
*co-authors
The 28th IEEE International Symposium on High-Performance Computer Architecture (HPCA-28)
Abstract
Repeated off-chip memory access to DRAM drive up operating power for data-intensive applications, and SRAM technology scaling and leakage power limits the efficiency
of embedded memories. Future on-chip storage will need higher density and energy efficiency, and the actively expanding field of emerging, embeddable non-volatile memory
(eNVM) technologies is providing many potential candidates to satisfy this need. Each technology proposal presents distinct trade-offs in terms of density, read, write, and reliability characteristics, and we present a comprehensive framework for navigating and quantifying these design trade-offs alongside realistic system constraints and application-level impacts. This work evaluates eNVM-based storage for a range of application and system contexts including machine learning on the edge, graph analytics, and general purpose cache hierarchy, in addition to describing a freely available (http://nvmexplorer.seas.harvard.edu/) set of tools for application experts, system designers, and device experts to better understand, compare, and quantify the next generation of embedded memory solutions.