Karthik Sangaiah, Drexel University
Michael Lui, Drexel University
Ragh Kuttappa, Drexel University
Baris Taskin, Drexel University
Mark Hempstead, Tufts University
In Proceedings of the 26th IEEE International Symposium on High-Performance Computer Architecture (HPCA 2020). February 2020. San Diego, CA.
In this work, we propose and evaluate a Network-on-Chip (NoC) augmented with light-weight processing elements to provide a lean dataflow-style system. We show that contemporary NoC routers can frequently experience long periods of idle-
time, with less than 10% link utilization in HPC applications. By repurposing the temporal and spatial slack of the NoC, the proposed platform, SnackNoC, is able to compute linear algebra kernels efficiently within the communication layer with minimal additional resource costs.
SnackNoC ‘Snack’ application kernels are programmed with a producer-consumer data model that uses the NoC slack to store and transmit intermediate data between processing elements. SnackNoC is demonstrated in a multi-program environment that continually executes linear algebra kernels on the NoC simultaneously with chip multiprocessor (CMP) applications on the processor cores. Linear algebra kernels are computed up to 6.15× faster on SnackNoC compared to an Intel Haswell EP x86 processing core. The cost of executing ‘snack’ kernels in parallel to the CMP applications is a minimal runtime impact of 0.01% to 0.83% due to higher link utilization, and an uncore area overhead of 1.1%.