Here is a list of even older Projects from Prof. Hempstead’s PhD student days. (Before he established the DPAC and TCAL labs) This includes work developing an energy efficiency architecture for wireless sensor networks, early-staged models for many accelerator architectures (Navigo), and power models for wireless sensor networks (PowerTOSSIM and Multihop Models).
| Power-Aware Architecture for Wireless Sensor Networks |
| Recent years have seen a burgeoning interest in embedded wireless sensor networks with applications ranging from habitat monitoring to medical applications. Wireless sensor networks have several important attributes that require special attention to device design. These include the need for inexpensive, long-lasting, highly reliable devices coupled with very low performance requirements. Ultimately, the “holy grail” of this design space is a truly untethered device that operates off of energy scavenged from the ambient environment. We taken an application-driven approach to the architectural design and implementation of a wireless sensor device that recognizes the event-driven nature of many sensor-network workloads. The chip has been taped out and measured.
Publications: [ISCA’05], [CASES’09],[JETCAS ’11] |
| Chips |
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Wireless sensor network test chip, ULP-1 in IBM 180nm CMOS. Implementation of our architecture that appears in Hempstead et al [1st Prize SRC SoC Design Contest!!]
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| Wireless sensor network test chip, ULP-2, UMC 130nm CMOS. Successfully demonstrates wireless sensor node design with better power-performance characteristics compared to any previously published work. [Die-photo pending publication] |
| Projects |
| Navigo: A Model to Study Power-Constrained Architectures and Specialization |
| Technology scaling has met a ceiling—power. As the number of transistors double, it becomes difficult to power all of them within a strict power budget and still achieve the performance gains of 1.58x per year that the industry has achieved historically. We have developed, Navigo, a model for architecture exploration across future process technology generations. Using parameters from existing commercial processor cores, we show how power consumption limits the theoretical throughput of future processors. Navigo shows that specialization is the answer to circumvent the power density limit that curbs performance gains and resume traditional 1.58x performance growth trends, because custom circuits designed to speed up specialized functions can provide orders of magnitude energy savings.[MOBS’09] |
| Architecture and Circuit Techniques for Low-Throughput, Energy-Constrained Systems Across Technology Generations |
| Rising interest in the applications of wireless sensor networks has spurred research in the development of computing systems for low-throughput, energy-constrained applications. Unlike traditional performance oriented applications, sensor network nodes are primarily constrained by operation lifetime, which is limited by power consumption. Advanced CMOS process technologies provide ever increasing transistor density and improved performance characteristics. However, shrinking feature size and decreasing threshold voltages also lead to significant increases in leakage current, which is especially troublesome for applications with significant idle times. This work investigates tradeoffs between leakage and active power for low-throughput applications.We study these issues across a range of process technologies on a computing architecture that provides explicit support for fine-grain leakage-control techniques such as Vdd-gating and adaptive body bias. We present a methodology for selecting design parameters, including choice of process technology, that makes the optimal tradeoff between active power and leakage power for a given workload. Our results show that leakage power will dominate the selection of process technology, and architectures that support advanced leakage control techniques at the circuit level will be essential. We argue that without advanced low power architectures future nano-scale process technologies will not be suited for sensor network applications.Publications: CASES’06 [PDF] |
| PowerTOSSIM: Simulating the Power Consumption of Large-Scale Sensor Network Applications |
| Developing sensor network applications demands a new set of tools to aid programmers. A number of simulation environments have been developed that provide varying degrees of scalability, realism, and detail for understanding the behavior of sensor networks. To date, however, none of these tools have addressed one of the most important aspects of sensor application design: that of power consumption. While simple approximations of overall power usage can be derived from estimates of node duty cycle and communication rates, these techniques often fail to capture the detailed, low-level energy requirements of the CPU, radio, sensors, and other peripherals. PowerTOSSIM, is a scalable simulation environment for wireless sensor networks that provides an accurate, per-node estimate of power consumption. PowerTOSSIM is an extension to TOSSIM, an event-driven simulation environment for TinyOS applications. In PowerTOSSIM, TinyOS components corresponding to specific hardware peripherals (such as the radio, EEPROM, LEDs, and so forth) are instrumented to obtain a trace of each device’s activity during the simulation run. PowerTOSSIM employs a novel code-transformation technique to estimate the number of CPU cycles executed by each node, eliminating the need for expensive instruction-level simulation of sensor nodes. PowerTOSSIM includes a detailed model of hardware energy consumption based on the Mica2 sensor node platform. Through instrumentation of actual sensor nodes, we demonstrate that PowerTOSSIM provides accurate estimation of power consumption for a range of applications and scales to support very large simulations.Publications: SenSys’04 [PDF] Collaborators: With Prof. Matt Welsh and the WSN Systems Group. |
| Analytical Power Modeling of Wireless Communication and Multi-hop vs. Single-hop Routing |
| A realistic power consumption model of wireless communication subsystems typically used in many sensor network node devices is presented. Simple power consumption models for major components are individually identified, and the effective transmission range of a sensor node is modeled by the output power of the transmitting power amplifier, sensitivity of the receiving low noise amplifier, and RF environment. Using this basic model, conditions for minimum sensor network power consumption are derived for communication of sensor data from a source device to a destination node. Power consumption model parameters are extracted for two types of wireless sensor nodes that are widely used and commercially available. For typical hardware configurations and RF environments, it is shown that whenever single hop routing is possible it is almost always more power efficient than multi-hop routing. Further consideration of communication protocol overhead also shows that single hop routing will be more power efficient compared to multi-hop routing under realistic circumstances. This power consumption model can be used to guide design choices at many different layers of the design space including, topology design, node placement, energy efficient routing schemes, power management and the hardware design of future wireless sensor network devices.Publications: SECON’06 [PDF] Collaborators: With Prof. Qin Wang and Prof. Woodward Yang |
