HSSB: HotSpots Strike Back

A Workshop on Cross-Stack Challenges and Techniques for Combating Advanced Hotspots


This workshop will bring together researchers across disciplines (devices, implementation, packaging, architecture, and systems) that are tackling problems of hotspots in current and future microprocessors and accelerators. The purpose is to demonstrate to the community the severity of advanced hotspots which can be found in current generation process technology nodes; these hotspots appear quickly (fast application-specific transients) and have gradients over 30°C (compared to nearby components). Solving such hotspots will require a cross-stack approach involving both implementation and design techniques as well as cooling and dynamic architecture techniques. The workshop will be organized mostly with invited speakers that the organizers bring from throughout industry and academia. In addition, there will be an open call for papers.

Workshop Organizers and Bios

  • Mark Hempstead (Tufts University) – Mark Hempstead is an Associate Professor at Tufts University. His research has been applied to a range of platforms from chip multiprocessors, high-performance computing, machine learning systems, embedded systems, and IoT. Dr. Hempstead received a BS in Computer Engineering from Tufts University and his MS and Ph.D. in Engineering from Harvard University prior to joining Tufts University in 2015, he was an Assistant Professor at Drexel University. He received the NSF CAREER award in 2014.
  • Alexander Hankin (Tufts University)  Alexander Hankin is a final-year Ph.D. student in the Electrical and Computer Engineering Department at Tufts University. His research interests include embedded non-volatile memories, thermal hotspots, and ion-trap quantum architectures. He received the BS and MS degrees in Computer Engineering and Electrical Engineering, respectively, at Tufts, and he has completed research internships at Google and Intel.
  • Julien Sebot (Intel) – Julien Sebot is a Senior Principal Engineer at Intel in Hillsboro. His areas of interest include processor architecture, performance modeling, and power and thermal analysis. He earned a Ph.D and MS degree from Paris-Sud University. 
  • Kaushik Vaidyanathan (Google) Kaushik is a chip implementation lead at Google. His work and interest span circuit design, physical design, design automation, emerging technologies, and architectures. He received his Bachelors from Madras Institute of Technology and his MS and Ph.D. in Electrical and Computer Engineering from Carnegie Mellon University. Prior to joining Google, Kaushik was a staff researcher at Intel Labs and a research engineer at IBM.
  • David Werner (Tufts University/TBD) Dave is currently in the final year of his PhD in the Electrical and Computer Engineering Department at Tufts University. His research interests revolve around identifying, modeling, and analyzing thermal concerns in modern ICs, including topics such as thermal side-channel analysis and hotspot characterization and mitigation. He completed his undergraduate studies at Drexel University where he received a B.S. in Computer Engineering and a B.S. in Electrical Engineering. He subsequently received his M.S. in Electrical Engineering at Tufts University. He has had internships at Coldlight Solutions, Micron, and Woodward McCoach as an undergrad, and MITRE as a graduate student.

Call For Papers

On-chip thermal hotspots are becoming one of the primary design concerns for next-generation processors. Industry chip design trends coupled with post-Dennard power density have led to a stark increase in localized and application-dependent hotspots. These “advanced” hotspots cause a variety of adverse effects if untreated, ranging from dramatic performance loss, incorrect circuit operation, and reduced device lifespan. In the past, hotspots could be addressed with physical cooling systems and EDA tools; however, the severity of advanced hotspots is prohibitively high for conventional thermal regulation techniques alone. Cross stack approaches that incorporate device, circuit, packaging, cooling, architecture, and software are needed.

HSSB: HotSpots Strike Back: seeks papers that study next-generation advanced on-chip thermal hotspots. Position papers and work-in-progress papers are encouraged. The organizers are interested in presenting a diversity of fields and approaches to thermal on-chip hotspots. 

List of Potential Topics

  • Packaging and system cooling approaches to hotspot mitigation
  • Data and retrospective studies characterizing hotspot behavior in simulation or silicon
  • Device, circuit, architecture studies that illustrate the challenges of hotspots and their impact on chip’s performance, cost, and reliability 
  • Tools (at the transistor, chip, package, and system abstractions) that characterize or model hotspot behavior
  • Hotspot aware predictions or mitigations at the circuit, architecture, or software level
  • Design automation (EDA) approaches to hotspot prediction and mitigation

Submission and Presentation Format

An abstract of at most 2 pages should be submitted that describes the problem, the study or the design to be presented at the workshop. The presentation format will include a 15-30 minute presentation. In addition, all speakers will be invited to join a panel discussion at the end of their session where questions from the audience and debate among panelists will be encouraged. 

Submit your abstract here.

Important Dates

Submission Due Date (Extended) May 1, 2022 May 5th, 2022
Author Notification (Updated)May 8, 2022 May 12th, 2022
Final Abstract Due Date: May 29, 2022
Workshop: Sunday, June 19th (morning session)